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Lattice Semiconductor
Functional Description
Additional Notes:
? The MAC Tx state machine may do other processing, such as inserting IPG after a previous packet is transmit-
ted, so even if tx_fifoempty is low and tx_fifoavail is high the MAC may not assert the tx_macread right away.
? There are many ways to interface client logic and FIFOs to the MAC - here are two examples:
1.) An appropriate threshold level for the Tx FIFO is chosen which indicates that a full frame is ready to be
sent. This is used as the tx_fifoavail signal. If there are variable size packets (some small) one may want to
OR this threshold with a frames_present signal. frames_present is a frames counter that keeps track of
EOPs into and out of the FIFO. Whenever the FIFO is Not Almost Empty and there is at least one full
packet in the FIFO tx_fifoavail is set high to indicate it is safe to transmit a packet.
2.) Decouple the tx_fifoempty and tx_fifoavail signals from the actual Tx FIFO and generate tx_fifoavail and
tx_fifoempty signals from a simple state machine:
I) Keep tx_fifoavail low and tx_fifoempty high - load Tx FIFO
II) When packet is fully loaded into Tx FIFO assert tx_fifoavail high and de-assert tx_fifoempty (set to
not empty)
III) When packet is completely pulled out of FIFO, de-assert tx_fifoavail and force tx_fifoempty high
Successful Transmission of a 64-byte Frame with FIFO Empty - Tx MAC Application Inter-
face
tx_fifoempty is asserted along with tx_fifoeof to indicate that the complete 64-byte frame has been read.
The frame is transmitted as a valid frame and tx_done is asserted at the end of transmission.
Figure 2-13. Successful Transmission of a 64-byte Frame with FIFO Empty
txmac_clk
tx_fifoavail
tx_fifodata[7:0]
1
2
62
63
64
tx_macread
tx_staten
tx_staten[31:0]
tx_fifoeof
tx_fifoempty
tx_discfrm
tx_done
Valid
IPUG51_03.0, December 2010
33
Tri-Speed Ethernet MAC User’s Guide
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